Hiring.Camp

Lead Application Engineer

Cadence Design

·

Yesterday

Salary
$92k – $172k
Location
HOME WA, United States of America · BURLINGTON 01 · CARY · AUSTIN · Burlington, MA
Type
Full-time
Department
Engineering
Seniority
Lead
Experience
15+ years
Education
Master
Source
Workday

Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This position involves defining and leading the development of advanced packaging and 3DIC analysis flows for foundry and customer solutions.

Location/s; remote role but must be located in the US.

The candidate will have expert knowledge of the Cadence toolset and/or equivalent competitor toolsets in the context of multiple flows including high-speed signal design, power design, signal integrity, power integrity and definition of electrical constraints. Design experience and industry knowledge of one of Signal, Power, and Thermal analysis associated with IC, package, or PCB design is required .

The candidate needs to have the ability to analyze the customer's environment and evaluate appropriate solutions. Be knowledgeable and aware of competitive technologies. Anticipates technical issues and develops creative solutions before they become a problem. Takes technical lead on a wide range of projects. Ability to understand high-speed, high-performance signal and power integrity-related issues, and work with peers and other business groups.  Able to communicate effectively with Cadence R&D, Product Engineering, Marketing and with customers. Understands customer success criteria and is committed to ensuring customer success. 

Position requires:
•    Bachelor’s degree (Masters preferred) in Electrical or Electronics Engineering with 
•    Minimum 15 years experience with Signal Integrity, Power Integrity, Electromagnetics, Thermal, and RF related to Package and PCB Design is required
•    5+ years experience with Cadence SI/PI tools Allegro platform tools including: Sigrity, Clarity, PCB Editor, ICP preferred
•    Strong knowledge of advanced packaging concepts
•    Strong knowledge of 2.5D, 3DIC and stacked die technologies
•    Understanding of chip level CMOS design concepts desired
•    Strong customer-facing communication and problem-solving skills
•    Strong personal drive for continuous learning and expanding professional skill sets
•    Excellent verbal and written communication skills


 

The annual salary range for Washington is $92,400 to $171,600. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

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Lead Application Engineer at Cadence Design • $92k – $172k | Hiring.Camp