Principal Physical Design Architect, HBM

Develop floorplans that optimize circuit placement, routing efficiency, and power delivery networks. Deliver block‑level analog or mixed‑signal layouts using advanced foundry process technologies. Collaborate with HBM architects and circuit designers on floorplanning, placement, routing, and integration strategies. Evaluate timing, area, power, and complexity trade-offs for high‑speed DRAM and mixed‑signal circuits. Support integration of Memory, Logic, and Analog circuits for new HBM product architectures. Ensure alignment with developed rules, manufacturability requirements, and physical verification constraints. Provide design-focused insights to improve circuit robustness, performance, and reliability. Participate in reviews and fixing issues across physical build, parasitic extraction, and full‑chip integration. MS degree with 5+ years of memory‑related layout or physical design experience, or BS degree with 7+ years of relevant experience. Expertise with Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS. Strong understanding of analog layout fundamentals including matching, EM, latch‑up, coupling, IR‑drop, crosstalk, and parasitic impacts. Hands‑on experience developing analog and mixed‑signal layouts (e.g., sense amplifiers, LDOs, PLLs). Strong analytical, problem‑solving, and collaboration skills. Experience working on DRAM, SRAM, or memory‑centric physical design. Ability to clearly communicate technical concepts to design, architecture, and verification teams. Motivated contributor who excels in team‑based, fast‑paced engineering environments.