Hiring.Camp

Intern - Verification Application Engineer

Cadence Design

·

Today

Location
PETAH TIKVA 01, Israel
Type
Internship
Department
Engineering
Seniority
Internship
Source
Workday

Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

As a Verification Application Engineer (AE) at Cadence you will be responsible for leading customer engagement solving verification challenges with leading edge technologies and methodologies.

You will be collaborating with key customers deploying advanced simulation flows in both RTL and GLS.   

This role has 2 main parts:

Pre-sale – join various technical campaigns presenting Cadence products and suggest appropriate solutions to customer requirements based upon these products. Post-sale - provide technical support of Cadence Functional Verification products

The AE will be expected to work independently and collaborate with other team members to address customer issues, identifying new opportunities or risks that are linked to those activities.
The AE will collaborate with R&D teams to influence the tools and methodology road maps based upon customer requirements.

At this position you will be able to improve your technical skills working with the industry leading engineers over a wide range of topics while interacting with the business world too.

This position requires a solid understanding of simulation-based verification flows such as RTL and GLS as well strong proficiency in Verilog/System Verilog/VHDL/Specman-e.

Requirements:

  • Student position with availability for 2–3 days a week (from office in Petach Tikva)
  • Electrical Engineering / Computer Engineering student in final year (1–2 semesters remaining)
  • GPA 85+ (or equivalent high academic performance)
  • Strong foundation in programming and scripting (any language – e.g. Python, C/C++, etc.)
  • Basic understanding of digital design / verification concepts
  • Knowledge in one or more of the following – advantage (not mandatory):
    • SystemVerilog / UVM
    • Verilog / VHDL
  • Motivation to learn and develop verification methodologies, protocols, and tools as part of the role
  • Soft skills: communicative, enjoys working with people, service-oriented, presentation skills
  • Strong verbal and written communication skills in English

We’re doing work that matters. Help us solve what others can’t.

Skills

Python

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