Semiconductor Principal Design Engineer, Non‑Volatile Engineering Group

Own internal NAND datapath circuits including array redundancy circuits, wave pipeline / pulse based datapath arctitechture and data line sensing circuits. Define scalable datapath architecture supporting multi-plane and high-parallelism operation. Define and analyse clock/data timing schemes for long interconnects and large-array topologies. Lead timing adjustment and skew management strategy. Drive layout-aware circuit design with attention to: matching/symmetry for sensing paths, shielding/guarding for sensitive nodes. Parasitic-aware sizing and RC-driven timing closure. Array pitch constraints, blockages and repeatable layout templates. Partner tightly with layout to review critical routes and implement practical fixes. Perform SPICE/Fast-SPICE simulations across PVT, aging and variability via Monte Carlo. Define characterization structures and debug plans to correlate silicon behavior vs. simulation. Drive root-cause analysis for margin/yield issues tied to datapath timing, redundancy paths or sensing robustness. Lead design reviews and unblock partners with clear technical decisions. Mentor other engineers; create reusable design collateral (checklists, templates, signoff methodology). Communicate tradeoffs effectively (PPA, margin, schedule, risk) and propose mitigation plans Communicate with project integration and other functional teams in design on specifications of major block interfaces BS or MS in Electrical Engineering with 8+ years of relevant experience Experience in physical design flows and optimization Proven ownership of blocks from concept -> design -> layout -> signoff -> silicon correlation, CMOS analog/mixed-signal circuit design and device physics fundamentals High-speed datapath timing analysis (including nontraditional timing such as wave-pipelined/pulse-based) Layout parasitics and physical implementation impact on circuit behavior Strong simulation and debug skills (SPICE/Fast-SPICE, corner/MC analysis, failure-mode thinking) Experience with managing complex design projects, effectively communicating progress and outcomes Direct experience in NAND datapath and/or DRAM datapath design. Wave-pipelining, self-timed, or pulse-latched pipeline design techniques Redundancy/repair architecture experience in dense arrays (including repair timing implications) Experience on DRAM interface(e.g. DDR4/5, LPDDR5/6, HBM3/3E/4) as well as other industry standard interfaces. Comprehensive understanding on CMOS device and device reliability