Hiring.Camp

ASIC Engineer

Cisco

·

Today

Salary
$155k – $223k
Location
USA-SAN JOSE, United States of America
Workplace
Onsite
Type
Full-time
Department
Engineering
Experience
3+ years
Education
PhD
Closing date
Today
Source
Workday

Description

The application window is expected to close on: 10/01/2026

Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

Meet the Team:

The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Key Responsibilities:

  • Develop, maintain, and enhance DFT CAD infrastructure and automation and Support DFT implementation flows like Scan insertion, ATPG generation, SPF generation, pattern simulation etc

  • Develop utilities and automation using Python, Perl, Tcl, and Shell scripting.

  • Debug DFT flow failures and work with design teams to resolve issues.

  • Create and maintain regression frameworks and dashboards.

  • Improve flow robustness, runtime, and scalability.

  • Support large-scale regressions on compute farms using LSF or equivalent job schedulers.

  • Develop documentation, FAQs, and onboarding material for internal users.

  • Support releases, tool qualification, and regression signoff.

  • Collaborate with DFT Design, ATPG, Verification, Physical Design, and CAD teams.

Minimum Qualifications:

  • Bachelor’s degree in Electrical or Computer engineering and 5+ years of ASIC Design experience or Master's degree in Electrical or Computer Engineering and 3+ years of experience, or PhD + 0 years of experience.

  • Experience with Verilog/SystemVerilog programming.

  • Experience with interactive and waveform debugging.

  • Experience with industry-standard DFT/EDA tools and ability to work closely with design, verification, and test teams to resolve flow and methodology issues.

  • Scripting experience in Python, Perl, TCL, or shell programming.

Preferred Qualifications:

  • Experience with Synopsys Design Constraints (SDC).

Why Cisco? 

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. 

We are Cisco, and our power starts with you. 

Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $155,000.00 to $222,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks.  Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:

  • 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees

  • 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco

  • Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees

  • Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)

  • 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next

  • Additional paid time away may be requested to deal with critical or emergency issues for family members

  • Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:

  • .75% of incentive target for each 1% of revenue attainment up to 50% of quota;

  • 1.5% of incentive target for each 1% of attainment between 50% and 75%;

  • 1% of incentive target for each 1% of attainment between 75% and 100%; and

  • Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area:

$155,000.00 - $256,000.00

Non-Metro New York state & Washington state:

$138,100.00 - $227,900.00

* For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.

** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

Skills

PythonPerl

Similar Jobs

30

ASIC Engineer

Nvidia · Bengaluru, KA,IN, IN +1

1 week ago

ASIC Engineer

Nvidia · India, Bengaluru +1

1 week ago

ASIC Engineer

Cisco · TWN-HSIN-CHU, Taiwan · Hybrid

3 weeks ago

ASIC Engineer

Cisco · ISR-TEL AVIV-YAFO, Israel +1 · Hybrid

1 month ago

ASIC Engineer

Cisco · ISR-TEL AVIV-YAFO, Israel · Hybrid

1 month ago

ASIC Engineer

Cisco · ISR-TEL AVIV-YAFO, Israel +1 · Onsite

2 months ago

ASIC Engineer

Cisco · IND-PUNE, India · Onsite

2 months ago

ASIC Engineer

Cisco · TWN-ZHUBEI, Taiwan · Hybrid

2 months ago

ASIC Engineer

Cisco · USA-SAN JOSE, United States of America · Onsite

2 months ago

Sr ASIC Physical Design Engineer

Nokia · United States, US · Onsite

Today

Staff ASIC Digital Engineer (FPGA Prototyping, Emulation, System-Level Debugging) with 8 to 12 years of experience

SanDisk · Bengaluru, KA, India

Yesterday

Staff ASIC Digital Engineer (SOC Verification, UVM) with 8 to 12 years of experience

SanDisk · Bengaluru, KA, India

Yesterday

Staff ASIC Model Engineer (C++, SystemC) with 8 to 12 years of experience

SanDisk · Bengaluru, KA, India · Hybrid

Yesterday

ASIC Design Engineer 2

Hewlett Packard Enterprise (HP) · Sunnyvale, California, United States of America · Onsite

Yesterday

ASIC Design Engineer 2

Hewlett Packard Enterprise (HP) · Sunnyvale, California, United States of America · Onsite

Yesterday

ASIC Design Engineer Intern

AMBARELLA · US Headquarters, United States of America

Yesterday

Entry Level ASIC/FPGA Design Engineer – Space Electronics - MTV

Boeing · USA - Mountain View, CA, United States of America · Onsite

Yesterday

ASIC Design Engineer 2

Hewlett Packard Enterprise (HP) · Sunnyvale, California, United States of America · Onsite

Yesterday

Senior Engineer I - ASIC Verification

Microchip · Malaysia - Penang (MCHP)

Yesterday

Senior Engineer I - ASIC Verification

Microchiphr · Malaysia - Penang (MCHP)

Yesterday

ASIC DFT Engineer

Cisco · IND-BANGALORE, India +2 · Hybrid

Yesterday

ASIC DFT Engineer

Cisco · IND-BANGALORE, India +2 · Hybrid

Yesterday

Senior ASIC Design Engineer

Hewlett Packard Enterprise (HP) · Bengaluru, Karnātaka, India · Onsite

Yesterday

Senior ASIC Design Engineer

Hewlett Packard Enterprise (HP) · Bengaluru, Karnātaka, India · Onsite

Yesterday

Entry Level ASIC/FPGA Design Engineer – Space Electronics - MTV

Boeing · USA - Mountain View, CA, United States of America · Onsite

Yesterday

Principal Engineer – ASIC SoC Design

Micron · Hyderabad - Phoenix Aquila, India

Yesterday

Senior ASIC Design Engineer

Hewlett Packard Enterprise (HP) · Bengaluru, Karnātaka, India · Onsite

Yesterday

Principal Engineer – ASIC SoC Design

Micron Technology · Hyderabad, TS,IN, IN

Yesterday

ASIC Design Engineer

Hewlett Packard Enterprise (HP) · Bengaluru, Karnātaka, India · Onsite

2 days ago

ASIC Design Engineer

Hewlett Packard Enterprise (HP) · Bengaluru, Karnātaka, India · Onsite

2 days ago