- Location
- Noida, India
- Workplace
- Hybrid
- Type
- Full-time
- Department
- IT
- Seniority
- Lead
- Experience
- 10+ years
- Source
- Workday
Description
Job Description (JD) – Senior LINT / CDC / RDC Verification Engineer (10-15 Years Experience)
Role
Technical Lead – LINT, CDC & RDC Verification
Experience
10-15+ Years in SoC/IP Design Verification, Signoff Methodology, and EDA Tool Deployment.
Location
Flexible / Hybrid
Job Summary
We are looking for a highly experienced LINT, CDC, and RDC Verification Expert to drive methodology development, qualification, deployment, and signoff across complex SoC and IP programs. The candidate should possess strong expertise in both Siemens Questa CDC/RDC/Lint and Synopsys VC SpyGlass (Lint/CDC/RDC) solutions and be capable of defining enterprise-wide signoff methodologies, debugging complex structural verification issues, and collaborating with design, DFT, safety, and CAD teams.
Key Responsibilities
Technical Leadership
- Define and maintain LINT, CDC, and RDC signoff methodologies for IP, Subsystem, and SoC development.
- Drive deployment and qualification of EDA solutions across multiple projects.
- Establish best practices, waiver management processes, and signoff criteria.
- Lead technical reviews and provide guidance on structural verification issues.
LINT Verification
- Perform RTL quality checks using Questa Lint and VC SpyGlass Lint.
- Analyze and resolve violations related to:
- Coding style
- Synthesis mismatches
- FSM issues
- Dead code
- X-propagation
- Clock/reset usage
- DFT-related checks
- Develop custom rule sets and methodology enhancements.
CDC Verification
- Execute CDC signoff using Questa CDC and VC SpyGlass CDC.
- Analyze:
- Clock domain crossings
- Synchronizer structures
- Reconvergence issues
- Data coherency checks
- Handshake protocol verification
- Asynchronous interface validation
- Drive CDC closure and root-cause analysis.
RDC Verification
- Lead Reset Domain Crossing analysis and signoff.
- Debug RDC violations, reset synchronizers, reset sequencing, and metastability risks.
- Collaborate with Design and Functional Safety teams to ensure robust reset architecture.
Methodology & Automation
- Develop Tcl/Python/Perl based automation for verification flows.
- Improve runtime, reporting, and dashboard generation.
- Create reusable verification infrastructure and deployment packages.
- Support CI/CD and regression integration.
Stakeholder Management
- Work closely with Design, DFT, Safety, CAD, and EDA vendors.
- Review tool roadmaps and evaluate new features.
- Mentor engineers and drive technical training programs.