Engineer, Advanced Packaging Development - Design Enablement & Layout

Req ID:

JR114465 Engineer, Advanced Packaging Development - Design Enablement & Layout

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Key Responsibilities:

• Develop and refine Design Rules, Requirements, and Test Structures for advanced packaging.
• Create layout and DBR test vehicle and product designs to support technology development.
• Ensure robust Design Rule Checks (DRC) and appropriate responses to deviations.
• Analyze large datasets to extract meaningful insights and drive data-driven decision-making.
• Leverage of artificial intelligence to reduce development time.
• Manage structure evaluation to support development and quantify process margins.
• Strategically partner with teams to resolve process issues related to layout and prioritize solutions.
• Document and communicate complex problem resolutions and drive cross-node design rule alignment.
• Maintain effective communication across Process Integration, Product Engineering, Design, and Advanced Mask teams.

Minimum Qualifications:

• BS/MS/PhD in Electrical Engineering, Microelectronics, Physics, or related field.
• 2+ years of experience in semiconductor industry in areas such as Process Integration, Yield Enhancement, Product Engineering, Design, Test Structure Development, or Unit Process Development.
• Very good understanding of semiconductor memory process flows and TSV based packaging.
• Hands on experience and proficiency in EDA tools (Cadence Virtuoso Layout and Schematic Editor, Calibre, Hspice etc.)
• Familiarity with Design Rule Characterization and validation on Silicon.
• Proficiency in programming languages such as Python, R, or MATLAB
• Capable of resolving complex technical issues and communicating clearly, with Exposure to CAD group interactions, data post-processing, and database/reticle data transfer.

Nice to have:

• Experience coding in SKILL or SVRF
• AI Agentic Workflow
• AI tool usage in layout design

Job Profile(s):

Semiconductor Design Engineer 2

Relocation Level: TBD

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