Hiring.Camp

Package Design Engineer

Broadcom

·

Sep 8, 2026

Apply
Location
USA-CA San Jose Innovation Drive, United States of America · USA-TX-Austin - River Place B7 · USA-Colorado-Fort Collins-4380 Ziegler Road
Workplace
Remote, Onsite
Type
Full-time
Department
Engineering
Education
PhD
Closing date
Today
Source
Workday

Description

Please Note:

1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)

2. If you already have a Candidate Account, please Sign-In before you apply.

Job Description:

Broadcom is seeking an IC package-design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs. You will be part of a worldwide R&D team developing high-performance package designs for ASICs for artificial intelligence (AI), networking, high-performance computing (HPC), and 5G base stations. These designs include SerDes at 224G and higher, 5G RF/Microwave ADC/DAC, HBM, DDR5 and more. You'll have the opportunity to collaborate with the team to create the package structures needed to enable new design, and contribute to efficiency improvements for our design team.

RESPONSIBILITIES:

  • Overall design responsibility for ASIC package designs, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts.

  • Package Design of critical structures for SerDes, ADC/DAC, DDR, etc.

  • Schedule, prioritize, & track your work across 2+ projects simultaneously

  • General flip-chip BGA package design & engineering

  • Project management and customer interface for your design projects

  • Contribute to efficiency improvements for the design team, through process development/improvement, automation, documentation, etc.

  • Physical design (layout) is a foundational responsibility in this role

 
EDUCATION/EXPERIENCE & REQUIREMENTS:

  • BSEE or similar field and 2+ years’ experience in flip-chip-BGA package design, including high-speed SerDes or MSEE or PhD

  • Knowledge of electrical engineering fundamentals

  • Preferred candidates have a working knowledge of package-level signal integrity and power integrity, to apply to package designs

  • Cadence APD (allegro package designer) experience is preferred. Equivalent layout tool is OK.

  • Cooperate with our world-wide team (multiple time zones), including co-design with internal team members and external (Vendor) designers

  • Self-management and organization skills

  • Preferred candidates will also have 1 or more years experience with Cadence SKILL for Allegro, or similar design-automation coding experience and interest

OTHER REQUIREMENTS

  • This job requires working on-site at the Broadcom office, 5 days a week. This is not a remote-work position.


Compensation and Benefits


The annual base salary range for this position is USD 82,500.00 To USD 132,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.


Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.


Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.


If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Skills

Project Management

Similar Jobs

30

Package Design Engineer

Job Listings·Eindhoven, North Brabant +1

1d ago

Package Design Engineer

Broadcom·Singapore-Yishun

1mo ago

Package Design Engineer

Broadcom·US·Remote, Onsite

2mo ago

Sr. IC Package Design Engineer (Silicon Engineering)

Spacex·Austin, Texas +1

3d ago

Sr. IC Package Design Engineer (Silicon Engineering)

Spacex·Austin, Texas +1

3d ago

Design Engineer- Package Integration

Cat·Lafayette, Indiana

4d ago

Staff IC Package Design Engineer

Renesas Electronics·Kaohsiung, Takao·Onsite

5d ago

Principal IC Package Design Engineer

"Ethernovia, Inc."·San Jose, California

6d ago

Principal Package Design Engineer

Renesas Electronics·Tempe, Arizona·Onsite

1w ago

ASIC Package Design Engineer

Broadcom·US·Remote, Onsite

1w ago

Sr Staff Package Design Engineer

Renesas Electronics·Bayan Lepas, Penang

1w ago

RF Package Design Engineer, Senior Staff

Qualcomm·San Diego, California

2w ago

(Sr.) Staff Package Design Engineer - MIS substrate/FC expose die (Experienced in Power or Gan is requried)

Renesas Electronics·Shanghai, China

2w ago

(Sr.) Staff Package Design Engineer - MIS substrate/FC expose die (Experienced in Power or Gan is requried)

Renesas Electronics·Suzhou, Jiangsu

2w ago

(Sr.) Staff Package Design Engineer - MIS substrate/FC expose die (Experienced in Power or Gan is requried)

Renesas Electronics·Kaohsiung, Takao

2w ago

(Sr.) Staff Package Design Engineer - MIS substrate/FC expose die (Experienced in Power or Gan is requried)

Renesas Electronics·Taichung, Taiwan

2w ago

(Sr.) Staff Package Design Engineer - MIS substrate/FC expose die (Experienced in Power or Gan is requried)

Renesas Electronics·Taipei, Taiwan

2w ago

(Sr.) Staff Package Design Engineer - MIS substrate/FC expose die (Experienced in Power or Gan is requried)

Renesas Electronics·Zhubei, Taiwan

2w ago

Staff Package Design Engineer

Renesas Electronics·Bengaluru, Karnataka·Hybrid

2w ago

Staff Package Design Engineer

Renesas Electronics·Bayan Lepas, Penang

2w ago

Staff Package Design Engineer

Renesas Electronics·Bangkok, Thailand

2w ago

IC Package Design Engineer

Cisco·Israel +1·Hybrid

3w ago

Principal Package Design Engineer

Renesas Electronics·Austin, Texas·Hybrid

1mo ago

Principal Package Design Engineer

Renesas Electronics·San Jose, California·Hybrid

1mo ago

Senior ASIC Package Design Engineer

K2Spacecorporation·Seattle, Washington

1mo ago

Senior ASIC Package Design Engineer

K2Spacecorporation·New York City, New York·Remote

1mo ago

Principal ASIC Package Design Engineer

K2Spacecorporation·Seattle, Washington

1mo ago

Principal ASIC Package Design Engineer

K2Spacecorporation·New York City, New York·Remote

1mo ago

Staff Package Design Engineer- experienced in package development of power SiP/module

Renesas Electronics·Zhubei, Taiwan

1mo ago

Staff Package Design Engineer - Cu FSM/BGBM/Bumping 封装设计专家

Renesas Electronics·Suzhou, Jiangsu

1mo ago