- Location
- Santa Clara, CA,US, US
- Type
- Full-time
- Department
- Engineering
- Experience
- 3+ years
- Education
- PhD
- Source
- Eightfold
Description
Minimum 3 years of DV experience using uvm/assertion based verification technologies Experience in verifying complex SOC or SOC subsystems Experience with caches and DDR memory protocol verification Experience with using memory verification VIP's Exposure to DDR phy Exposure to firmware/driver development using c++ Exposure with multiple succesfull tapeouts from conception to post silicon debug Exposure to Formal verification Exposure to PASIM simulations Exposure to perf and power verification. Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field.
