ASIC design verification Engineer/Senior

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Company:

Qualcomm China

## Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Requirements:

• Familiar with ASIC development, especially ASIC verification using System Verilog / UVM, SVA and Coverage-driven methodology, Emulation / FPGA validation
• Familiarity with Ethernet switching concepts, such as:
• L2/L3 forwarding, bridging, routing
• Packet processing pipelines
• Basic QoS (queuing, scheduling)
• Scripting skills (C/C++, Tcl, Perl) preferred
• Excellent teamwork, interpersonal and communication skills.
• Fluent in Chinese and English both verbal and written.
• Ability to work in stressful situations with tight schedules to meet.

Description of Function & Responsibility

• Develop testbench/testcases for Ethernet switch verification from Module level to Subsystem level
• Work with Arch/design team on micro-architecture and RTL design of networking blocks, testplan and verification closure
• Support Design/VI team on pre and post silicon debug
• Mentor junior engineers and guide best engineering practices

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

OR

Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field.

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