Senior layout Engineer – DPG Layout

Req. ID:

JR105996 Senior layout Engineer – DPG Layout

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Job Description

Role and Responsibilities

• Own the development and physical implementation of critical analog, mixed‑signal, and custom digital blocks, including block‑level and full‑chip layout ownership.

• Lead layout implementation using AI‑assisted and automated workflows, applying copilot‑based assistants, agentic AI flows, and rule‑aware automation to accelerate placement, routing and optimization.

• Perform and automate layout verification activities, including DRC, LVS, Antenna, Yield, ESD, TOTEM, EM/IR and quality checks.

• Drive on‑time delivery of blocks and partition‑level layouts with predictable quality and risk prediction/mitigation plans.

• Develop and deploy AI‑enabled methodologies for Semi-automated floorplanning, parasitic estimation, layout consistency checks and best‑practice enforcement, repetitive layout task elimination via SKILL, Python, TCL or agent‑based flows.

• Demonstrate technical leadership in planning, area and cycle‑time estimation, delegation and execution.

• Guide and mentor engineers in Analog layout fundamentals, Automation‑first approach, Design‑for‑quality and design‑for‑yield practices

• Collaborate closely with Design, CAD, Verification, Reliability, and Program Management teams, clearly communicating technical risks, schedule impacts and any optimization opportunities.

• Drive continuous improvement by identifying manual bottlenecks and converting them into scalable automated flows.

Job Requirements

• 6+ years of experience in analog/custom layout design in advanced CMOS technology nodes.

• Strong expertise in Cadence Virtuoso (VLE/VXL) and Calibre DRC/LVS, with hands‑on ownership of verification closure.

• Proven experience in layout of critical analog blocks, including but not limited to Temperature sensors, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, Charge pumps, etc

• Hands‑on experience with memory layouts, including DRAM, SRAM, CAM, OTP and understanding of array‑to‑periphery integration.

• Deep understanding of analog layout fundamentals, including Matching and symmetry, EM, latch‑up, coupling, crosstalk, IR‑drop, shielding, guard‑ring strategies, parasitic effects.

• Strong ability to interpret design intent and constraints and translate them into high‑quality, manufacturable layouts.

• Proven expertise in defining, developing, and scaling AI‑driven automation and AI‑assisted methodologies for complex layout workflows.

• Demonstrated problem‑solving skills in physical verification, debug, and layout optimization dedicated to improving yield.

Education

• B.Tech in Electronics, Electronics & Communication, or VLSI Engineering

• M.Tech in VLSI Design, Microelectronics, or Electronics Engineering

Job Profile(s):

Semiconductor Design Engineer 3

Relocation level: (TBD)

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As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.