Senior Layout Engineer

Highly autonomous engineer with 5–8 years of experience spanning unit-cell to complex chip-level layout implementation and physical verification. This role balances rigorous technical execution, client management, deep DRM knowledge, and workflow innovation (BKMs) with active team leadership—overseeing task delegation, driving post-mortems, mentoring talent, and maintaining high-value client relationships to ensure on-time, high-quality delivery.
 

Technical Execution & Verification Sign-Off

• Unsupervised Layout Implementation: Independently execute layout designs across all hierarchies—from unit cells and blocks to complex MACRO, PHY, and full-CHIP levels—without supervision.

• Autonomous Physical Verification: Own the complete verification flow (DRC, LVS, etc.). Ensure all results are double-checked, remaining errors are formally waived/confirmed, and comprehensive documentation is provided.

• Architectural Mastery & Compliance: Maintain deep ownership of assigned architectures and Design Rule Manuals (DRM) across various process technologies (planar CMOS, FinFET, and advanced nodes).

Workflow Innovation & Efficiency

• BKM Optimization: Independently develop and implement test cases to achieve optimal technical solutions in the shortest timeframe while continuously improving Best-Known Methods (BKMs).

• Project Improvement Planning: Proactively develop, implement, and innovate project improvement plans to ensure timely, cost-effective, and high-quality silicon output.

Leadership, Delegation & Continuous Improvement

• Operational Management: Manage and lead tasks, engineering groups, or projects. Drive the efficient implementation of task assessment, delegation, execution, review, and final submission.

• Challenging the Status Quo: Actively evaluate and challenge existing workflows, documentation, and processes to guarantee long-term operational success.

• Post-Mortem Integrity: Initiate and implement post-mortem reviews, ensuring all action items are closed out and robust technical/procedural countermeasures are developed.

Meta Competencies

• Technical Autonomy & Decisiveness: The ability to navigate extreme layout complexity and independently sign off on physical verification risks without requiring oversight.
• Constructive Disruption (Change Leadership): A proactive mindset that routinely challenges legacy workflows and documents to optimize long-term engineering efficiency.
• Operational Agility & Speed: Exceptional capability in accelerating the task lifecycle—rapidly deploying test cases and managing engineering resources under tight timelines without compromising quality.
• Bi-Functional Leadership: The ability to pivot seamlessly between highly analytical micro-level engineering and macro-level human management (coaching, team development, and client relations).

Requirements:

• Bachelor’s or Master’s degree in Electronics Engineering, Electrical Engineering, or a related field, with a specialization in Integrated Circuit (IC) design.

• 5–8 years of relevant, hands-on experience in analog/mixed-signal or digital IC layout design and full-chip physical verification