Principal HBM Design Architect

Design and analyze digital, analog, and mixed‑signal circuits for HBM DRAM products. Perform schematic entry, simulation, and optimization of DRAM blocks including data path, ECC, command control, and clocking circuits. Evaluate full‑chip and block‑level functionality and deliver solutions ensuring functional accuracy. Conduct pathfinding and feasibility studies for next‑generation HBM architectures. Optimize circuit timing, area, power, and complexity across high‑speed DRAM designs. Support design floor planning, layout reviews, and cross‑domain integration of memory, logic, and analog circuits. Collaborate with global engineering teams to drive innovation and support vertical integration across design, validation, and manufacturing. Contribute to verification and validation strategies for highly complex HBM systems. BSEE with 7+ years of relevant engineering experience, or MSEE with 5+ years of relevant engineering experience. Strong knowledge of CMOS circuit design and semiconductor device physics. Hands‑on experience with schematic entry and simulation tools such as Finesim and HSPICE. Experience with power distribution and power network analysis. Proficiency with scripting languages such as Python, Tcl, or Perl. Familiarity with DRAM or memory design fundamentals. Excellent analytical and problem‑solving skills with the ability to address complex design challenges. Strong communication and collaboration skills with the ability to clearly convey technical concepts.