Senior Layout Engineer - DPG Layout

Req. ID:

JR101985 Senior Layout Engineer - DPG Layout

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Role and Responsibilities

• Implement the design and physical implementation of analog, mixed‑signal, custom digital blocks and support full‑chip integration, using a combination of traditional layout expertise.
• Own block‑level layout execution with strong focus on quality, turnaround time and design intent.
• Perform layout verification activities, including DRC, LVS, Antenna checks, Yield and quality checks.
• Deliver on‑time, high‑quality block‑level layouts under the guidance from senior engineers.

• Use prompt‑based AI tools to Generate or refine SKILL/Python/TCL scripts, automate repetitive layout and verification tasks to reduce manual effort and improve layout consistency.

• Support custom and digital layout integration, using semicustom tools to accelerate ECOs, alignment, and integration‑level updates.
• Collaborate closely with Design, Verification, CAD, and senior layout engineers, clearly communicating layout status and risks.

• Assist in reviewing sub‑block layouts from engineers developing their skills and share helpful techniques within the team.

Job Requirements

• 3+ year experience in analog/custom layout design in advanced CMOS process.
• Hands‑on experience with Cadence Virtuoso (VLE/VXL) and Calibre DRC/LVS, including ownership of verification and closure for assigned blocks.

• Experience in layout of critical analog and mixed‑signal blocks like Temperature sensors, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, Charge pumps
• Exposure to memory layout environments, including DRAM, SRAM, CAM or OTP is desirable.

• Solid understanding of analog layout fundamentals, including Matching and symmetry techniques electromigration, latch‑up, IR‑drop, Coupling, crosstalk and parasitic effects.

• Understanding of layout impact on circuit performance, including speed, capacitance, power, and area.
• Ability to interpret design constraints and translate them into robust, manufacturable layouts.
• Hands‑on experience in developing or applying AI‑driven automation and AI‑assisted methodologies to improve efficiency and quality of physical layout tasks.
• Strong problem‑solving skills in physical layout verification and debug.

Education

• B.Tech in Electronics, Electronics & Communication, or VLSI Engineering
• M.Tech in VLSI Design, Microelectronics, or Electronics Engineering

Job Profile(s):

Semiconductor Design Engineer 3

Relocation level: (TBD)

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As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.